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VHDL
What is VHDL?
VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems.
VHDL has many features appropriate for describing the behavior of electronic components ranging from simple logic gates to complete
microprocessors and custom chips. Features of VHDL allow electrical aspects of circuit behavior (such as rise and fall times of signals,
delays through gates, and functional operation) to be precisely described. The resulting VHDL simulation models can then be used as
building blocks in larger circuits (using schematics, block diagrams or system-level VHDL descriptions) for the purpose of simulation.
VHDL is also a general-purpose programming language: just as high-level programming languages allow complex design concepts to be
expressed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic
circuit synthesis or for system simulation. Like Pascal, C and C++, VHDL includes features useful for structured design techniques, and
offers a rich set of control and data representation features. Unlike these other programming languages, VHDL provides features allowing
concurrent events to be described. This is important because the hardware described using VHDL is inherently concurrent in its operation.
One of the most important applications of VHDL is to capture the performance specification for a circuit, in the form of what is commonly
referred to as a test bench. Test benches are VHDL descriptions of circuit stimuli and corresponding expected outputs that verify the
behavior of a circuit over time. Test benches should be an integral part of any VHDL project and should be created in tandem with other
descriptions of the circuit.
A standard language
One of the most compelling reasons for you to become experienced with and knowledgeable in VHDL is its adoption as a standard in the
electronic design community. Using a standard language such as VHDL virtually guarantees that you will not have to throw away and
recapture design concepts simply because the design entry method you have chosen is not supported in a newer generation of design tools.
Using a standard language also means that you are more likely to be able to take advantage of the most up-to-date design tools and that
you will have access to a knowledge base of thousands of other engineers, many of whom are solving problems similar to your own.
A brief history of VHDL
VHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed in the early 1980s as a
spin-off of a high-speed integrated circuit research project funded by the U.S. Department of Defense. During the VHSIC program,
researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large
circuit design problems that involved multiple teams of engineers. With only gate-level design tools available, it soon became clear that
better, more structured design methods and tools would be needed.
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