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Verilog
What is Verilog?
Verilog HDL is a hardware description language used to design and document electronic systems.
Verilog HDL allows designers to design at various levels of abstraction. It is the most widely
used HDL with a user community of more than 50,000 active designers.
A Brief History
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985.
The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm.
Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first
Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought.
Rumors abound that there were merger discussions between Gateway and Synopsys in the early days,
where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages
like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language.
VHSIC it self stands for "Very High Speen Intergrated Circuit" ).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990,
and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language,
being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on
Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to
market in 1992, and now there are mature Verilog simulators available from many sources.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE
Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001.
Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Subsequently, a new working group was formed, IEEE P1800, to build on the IEEE 1364 language along with
additional contributions from Accellera. In mid 2004 the IEEE 1364 committee was disbanded, and maintenence
on the standard was taken up by the IEEE 1800 working group.
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